1. Field of the Invention
The present application relates to the field of nonvolatile NAND memory, and particularly to nonvolatile NAND memory having a 60 nm pitch or less.
2. Description of Related Art
With 90 nm design rule cells, a NAND nonvolatile memory storing charge on floating gates has the problem of parasitic capacitance between the floating gates of neighboring cells in the NAND nonvolatile memory. A solution to this problem of parasitic capacitance between neighboring floating gates, is the use of air spacers between the floating gates of neighboring cells of the NAND nonvolatile memory. This solution is discussed in, for example, US Patent Application Publication 2008/0283898, which cites Daewoong Kang et al., “Improving the Cell Characteristics Using Low-k Gate Spacer in 1 Gb NAND Flash Memory”, 2006 International Electron Devices Meeting, Technical Digest, December 2006, all of which are incorporated by reference.
NAND nonvolatile memory has advanced with the use of charge trapping material such as silicon nitride, to replace the floating gate. The floating gate is heavily doped polysilicon, a highly conductive equipotential material. In contrast with the floating gate, a charge trapping gate such as silicon nitride is a dielectric, and not a highly conductive equipotential material. Because charge trapping NAND nonvolatile memory does not rely on floating gates to store charge, charge trapping NAND nonvolatile memory does not have parasitic capacitance between neighboring floating gates. Accordingly, charge trapping NAND nonvolatile memory does not need air spacers between neighboring cells of the NAND nonvolatile memory, to address parasitic capacitance between neighboring floating gates.
The paper by Kang et al. discloses a memory cell with an aspect ratio, or ratio of gate height to channel width, of about 1. Because of the relatively wide trench between neighboring memory cells, this paper discloses the necessity of many steps to form an air gap between neighboring memory cells.
Another NAND nonvolatile memory advance is the continued scaling of size. NAND nonvolatile memory at sub-20 nm and sub-30 nm sizes have been successfully fabricated and characterized. Hang-Ting Lue et al., “Scaling Evaluation of BE-SONOS NAND Flash Beyond 20 nm”, 2008 Symposium on VLSI technology, Digest of Papers, June 2008, incorporated by reference. At these sizes and lower sizes, techniques such as double patterning can be applied to manufacture NAND nonvolatile memory. Yi-Shiang Chang et al., “Pattern Decomposition and Process Integration of Self-Aligned Double Patterning for 30 nm Node NAND FLASH Process and Beyond”, Optical Microlithography XXII, Proceedings of the SPIE, Volume 7274, pp. 72743E-1-72743E-8, 2009; Huixiong Dai et al., “Implementing Self-Aligned Double Patterning on Non-Gridded Design Layouts”, Proceedings of the SPIE, Volume 7275, pp. 72751E1-72751E-11, 2009; Andrew J. Hazelton et al., “Double patterning requirements for optical lithography and prospects for optical extension without double patterning”, J. Micro/Nanolith. MEMS MOEMS, Vol. 8, pp. 011003-1-011003-11, 2009; all incorporated by reference.